1. Field of the Invention
The present invention relates to electronic circuits dealing with high speed digital signals, in particular, it provides a circuit to reform or reshape distorted digital signals on transmission lines in integrated circuits (ICs) or large scale integrated (LSI) circuits.
2. Description of the Prior Art
In several recent semiconductor devices, a poly-silicon (polycrystalline silicon) layer has been used for internal wiring. For example, static RAM (Random Access Memories) word lines are usually formed from a poly-silicon layer. The poly-silicon word lines allow elimination of a double layer aluminum wiring line structure and decreases the height of bumps at the cross-over points of the word lines with bit lines which are also usually formed as an aluminum wiring layer. The height difference of the bumps at the cross-over points causes problems such as lower reliability and low yield for the manufactured devices. Furthermore, when both word lines and bit lines are fabricated of aluminum, the thermal treatment margin during the manufacturing process becomes narrow. All the above disadvantages increase device design difficulties and decrease design freedom.
In situations where wiring lines are used which do not require very low resistance, the poly-silicon wiring layer provides advantages despite its low conductivity as compared to aluminum, and this is the primary reason that poly-silicon is used for word lines in static RAMs. Further benefits, such as a simplified manufacturing process and improved yield are also provided by using poly-silicon wiring lines, since lines can be formed along with other IC elements using the normal processes for fabricating the devices.
In order to avoid the relatively high resistivity of poly-silicon wiring, it is necessary to make the wiring lines wide, however, this increases the capacitance of the lines. The large resistance and capacitance of poly-silicon lines distorts transmitted signals and increases the delay in the rise and/or fall time of the transmitted signals. As a result, the logic speed decreases and operational errors by the device increase. For example, about 60 to 70 nanoseconds of delay is inevitable in the signals on poly-silicon word lines for a prior art state-of-the-art 64 K bit static RAM.
FIG. 1A is a schematic diagram of a prior art poly-silicon wiring line, and FIG. 1B is a graph of signal waveforms at the points "a" and "b" in FIG. 1A. In FIGS. 1A and 1B, a square wave digital signal (curve a) is supplied to an input end "a" of a network from a signal source(S) 101, a word line driver, for example. The signal is distorted (as shown by curve b) while passing along a long wiring line, such as a poly-silicon word line in a static RAM, for example. The poly-silicon wiring line can be considered as a distributed equivalent constant circuit consisting of a resistance 102 and a capacitance 103. The resistance 102 is inherent in the poly-silicon wiring line, while the capacitance 103 represents the total capacitance of the line including the capacitance of the components attached to the poly-silicon wiring line and the capacitance between the substrate of the IC and the wiring line, etc.
Recent ICs or LSIs require a delay time on the order of 10 nanoseconds or less and, as the integration density gets higher, the wiring lines become finer and longer. These problems make poly-silicon wiring layers difficult to use in these applications. One approach in solving the delay problem is to provide a poly-silicon layer having a lower resistivity. With this approach, an improvement of only a fifty percent reduction in terms of the delay time has been achieved. Another approach is to provide circuitry which cuts off the tail of the delayed signals using a gate attached at the end of each wiring line. This approach cannot improve rise time, is ineffective for longer wiring lines and has the drawback of requiring clock measurements. Consequently, a breakthrough in poly-silicon layer wiring is needed to overcome the delay time problems associated with increased integration of ICs and LSIs.